module dyndisp (clk_disp,rst,h2,h1,m2,m1,s2,s1,qhms,qnum);
	input clk_disp;
	input rst;
	input [3:0] h2;
	input [3:0] h1;
	input [3:0] m2;
	input [3:0] m1;
	input [3:0] s2;
	input [3:0] s1;
	
	output reg [3:0] qhms;
	output     [2:0] qnum;
	
	wire       [2:0] qnum1;
	assign           qnum=qnum1;
	
	counterN #(4'd6) controltime(    // 6个数码管
			.clk(clk_disp),
			.rst(rst),
			.sel(1'b0),
			.q1(qnum1));
			
	always @ (*)//qnum1[2] or qnum1[1] or qnum1[0]
	begin
		case (qnum1)
		3'd0:qhms=s1;
		3'd1:qhms=s2;
		3'd2:qhms=m1;
		3'd3:qhms=m2;
		3'd4:qhms=h1;
		3'd5:qhms=h2;
		default:qhms=3'd0;
		endcase
	end
	
	
endmodule 